1. Field
An aspect of the present disclosure relates to a page buffer and a memory device having the same and, more particularly, to a page buffer and a memory device having the same, which can reduce a sensing time in a read operation or a verify operation of the memory device.
2. Description of the Related Art
A memory system includes a memory device for storing data and a memory controller for controlling the memory device.
The memory controller controls the overall operations of the memory device, and also all command and data exchanges between a host and the memory device.
The host may communicate with the memory system by using an interface protocol, such as a peripheral component interconnect-express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), or a serial attached SCSI (SAS).
The memory controller controls the memory device in response to a host command received from the host. A plurality of storage devices included in the memory device may be operated simultaneously. However, when multiple operations requiring a large amount of current are simultaneously performed in a plurality of storage devices, the overall current consumption of the memory system may increase substantially at a rapid pace. Such spikes of current consumption may lead to an erroneous operation of the memory device due to a temporary current shortage. Therefore, the reliability of the memory system may be lowered.